1. Field of the Invention
The invention relates to a PMOS transistor of a semiconductor device, which exhibits improved characteristics, a semiconductor device incorporating the same, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
As a result of ongoing high integration and refinement of semiconductor devices, there is a continuous need for enhancement in characteristics of transistors. Particularly, in order to further improve capacitance, it has been attempted to develop a thinner gate insulation film which comprises an insulation material such as silicon oxide (SiO2).
However, reduction in thickness of the gate insulation film can cause direct tunneling, which increases current leakage, thereby causing several problems such as increase of power consumption, significant decrease in reliability of the gate insulation film, and so on.
In the related art, there are attempts to form a gate insulation film using an insulation material having higher dielectric constant than that of silicon oxide in order to secure a sufficient thickness of the gate insulation film while further enhancing the capacitance. One of the attempts is to form a gate insulation film using a hafnium-based oxide.
In this case, it is known that performance of the transistor deteriorates due to shift of a threshold voltage when applying a gate conductive film comprising polysilicon thereto (see Electronic Journal July 2005). For example, an NMOS transistor requires a threshold voltage of about 0.2 V to about 0.3 V, and a PMOS transistor requires a threshold voltage of about −0.2 V to about 0.3 V. However, when the gate insulation film is formed of a hafnium-based oxide, followed by applying a gate conductive film comprising polysilicon thereto, the threshold voltage of the PMOS transistor is shifted by about 0.6 V to about 0.7 V, and the threshold voltage of the NMOS transistor is also shifted by about 0.2 V to about 0.25 V, thereby deteriorating the performance of the transistor.
Fermi level pinning can be mentioned as one of major causes of the threshold voltage shift. Although the detailed mechanism of the Fermi level pinning has not yet been clearly described, many opinions report that it is directly caused by reaction between silicon and hafnium at an interface between the gate conductive film comprising the polysilicon and the gate insulation film formed of the hafnium-based oxide film. In other words, electrons are formed along with holes in the gate insulation film due to junction of silicon and hafnium, and move towards the polysilicon, thereby creating interfacial polarization. As a result, Fermi level pinning occurs from the gate insulation film comprising polysilicon so that the threshold voltage is shifted, thereby deteriorating performance of the transistor. In particular, such a phenomenon is remarkable in the PMOS transistor which comprises p-type polysilicon, and the gate conductive film comprising the same.